A direct conversion RF receiver (DCR) may be used to demodulate an incoming signal by mixing it with a local oscillator (LO) synchronized in frequency to a carrier wave of a wanted signal. A DCR may also be referred to as a zero intermediate frequency (IF) receiver.
DCR architectures have been widely adopted due to their high integration levels, low costs on complementary metal oxide semiconductor (CMOS) processes, and flexibility in implementing multi-standard receivers. One of the fundamental difficulties with a DCR is that IMD2 may cause signal quality degradation under strong blocker conditions.
High second order linearity may be desired to avoid signal to noise plus distortion ratio (SNDR) degradation by IMD2. For example, a second order intercept point (IP2) of 65 decibels referenced to milliwatt (dBm) or greater may be desired to detect a −82 dBm 54 megabit per second (Mb/s) signal (e.g., a 802.11g signal) in the presence of wireless code division multiple access (WCDMA) blocker. A good RF/analog design alone may not guarantee such a high IP2. This is due to the fact that IP2 depends on not only RF/analog design but also blocker frequency, local oscillator (LO) frequency, power supply voltage, ambient temperature variation, etc. IP2 may ultimately be limited by matching requirements, which may not be met with high yield for IP2 above 35-40 dBm without adjustment.